Ex Parte TUTTLE et al - Page 8




          Appeal No. 2000-1259                                                            
          Application 08/815,894                                                          

               For the foregoing reasons, the rejection of claim 43 and its               
          dependent claims 44 and 52-56 based on Dudley is reversed.  For                 
          the same reasons, so too is the rejection of independent method                 
          claim 57, which similarly recites "reconfiguring the timing                     
          recovery circuit and the gain control circuit before the sequence               
          detector finishes processing the discrete time sample values of a               
          current sector so that the read channel can begin acquiring an                  
          acquisition preamble of a next sector, thereby reducing a                       
          physical gap between sectors on the magnetic disk medium," and                  
          its dependent claims 58-63.                                                     
               Turning now to Figure 2 of Petersen, Appellants do not deny                
          that the claimed timing recovery circuit reads on data                          
          synchronizer 67, that the claimed gain control circuit reads on                 
          automatic gain control circuit 51, and that the claimed sequence                
          detector reads on pulse detector 63 in combination with encoder                 
          and decoder 73 (Answer at 3).  We note that control signal SGT                  
          (Figure 3(B)) causes each of automatic gain control circuit 51,                 
          filter system 55, and pulse detector 63 to be configured in one                 
          way during servo burst intervals (signal portion 143 in                         
          Figure 3(A)), while control signal RGT causes each of those                     
          circuits to be configured in another way during data intervals                  
          (signal portions 141 and 154 in Figure 3(A)).  Id. at col. 6, ll.               
          11-24 and 42-66; col. 9, ll. 14-31 and 58-64.  However,                         
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