Appeal No. 2000-1483
Application No. 08/851,608
The invention is directed to a trench DMOS transistor cell.
The gate region is positioned in the trench "that extends from
the top surface of the structure downward, using a three-
dimensional cell geometry that maximizes the gate dielectric
breakdown voltage and also provides position of voltage breakdown
initiation to allow use of controlled bulk semiconductor
breakdown" (specification, page 2).
Representative independent claim 17 is reproduced as
follows:
17. A trench DMOS transistor cell, comprising:
a substrate of a first conductivity type, said
substrate having a surface;
an epitaxial layer of said first conductivity type
formed on said surface of said substrate, said epitaxial
layer having a top surface and a bottom surface, said
epitaxial layer having a substantially uniform initial
dopant concentration at formation;
a body region of a second conductivity type formed in
said epitaxial layer, said body region extending, as
measured from said top surface of said epitaxial layer, to a
first depth dmax at a first location and to a depth of d at a
second location, where d is less than dmax, said first and
second locations being separated by a predetermined
horizontal distance;
a source region of said first conductivity type formed
in said expitaxial [sic] layer above a portion of said body
region, said portion of said body region being located
between said second location and said source region; and
-2-
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