Appeal No. 2000-1483
Application No. 08/851,608
a trench formed in said epitaxial layer, having
substantially vertical side walls, extending from said top
surface of said epitaxial layer to a depth dtr, said depth
dtr being less than said depth dmax, and greater than said
depth d, said trench being (i) closer to said second
location than said first location, and (ii) horizontally
adjacent said source region;
wherein breakdown in said trench DMOS transistor occurs
across said epitaxial layer at a position closer to said
first location than said second location.
The examiner relies on the following references:
Jambotkar 4,165,700 Mar. 20, 1979
Tonnel 4,420,379 Dec. 13, 1983
Daisuke Ueda et al. (Ueda), "A New Vertical Power MOSFET
Structure with Extremely Reduced On-Resistance," ED-32 IEEE
Transactions on Electron Devices no. 1, 2-6 (January 1985)
Kikuo Yamabe et al. (Yamabe), "Nonplanar Oxidation and Reduction
of Oxide Leakage Currents at Silicon Corners by Rounding-off
Oxidation," ED-34 IEEE Transactions on Electron Devices no. 8,
1681-87 (August 1987)
Claims 17-21, 25-37, 39-41, 44, 46-58, 60-62, 64 and 65
stand rejected under 35 U.S.C. § 103. As evidence of
obviousness, the examiner offers Tonnel and Ueda with regard to
claims 17-21, 25-29, 32-37, 44, 46-58, 64 and 65, adding
Jambotkar with regard to claim 30 and further adding Yamabe with
regard to claims 31, 39-41 and 60-62.
Reference is made to the brief and answer for the respective
positions of appellants and the examiner.
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