Appeal No. 2000-1939
Application 08/791,281
Appellants' solution, shown in Figure 7, reproduced below,
is to connect an additional capacitance CY which between the
common terminal (node B) of switch SW3 and ground.
The specification
explains that
[b]y suitably sizing the capacitor CY so that its
capacitance is much higher than the parasitic
capacitance Cp of the node B and that its equivalent
impedance is much lower than the conduction resistance
Ron of the transistors at a frequency equal to the
inverse of the decay time of the clocking signals used
to drive the switch transistors, the overall impedance
as seen from the circuit node B toward ground can be
linearized.
Id. at 8, lines 26-33. As a result, the amount of charge
injected into capacitor C3 by transistor M4 when it turns off is
constant, thereby resulting in a constant voltage offset in the
output signal but no system harmonic distortion. Id. at 10,
lines 13-24.
Figure 6, reproduced below, shows this technique, using
capacitors CX and CY, applied to nodes A and B of the switched
-5-
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007