Appeal No. 2000-1939
Application 08/791,281
1/1000 of the frequency of complementary clock signals N1 and N2,
thereby connecting the capacitor terminal to ground and
discharging the capacitor to reinitialize the integrator (col. 4,
l. 42 to col. 5, l. 9). During time T2, clock signal N3 goes
low, opening switch 26, and clock signal N2 goes high, closing
switch 24 (col. 5, ll. 29-34), thereby connecting the switched
capacitor terminal to output terminal 21 of operational
amplifier 19.
At time T3, N2 goes low, opening switch 24 (col. 5, ll. 53-
54). However,
[d]uring the periods when N2 is low and thus switch 24
is off, leakage currents through switch 24 tend to
discharge capacitor 23. By the use of capacitor 22
connected to node 70, capacitor 22, as well as
capacitor 23, is partially discharged due to the
leakage currents through non-conducting switch 24. By
the proper sizing of capacitor 22, the effect of
leakage currents through switch 24 on the charge stored
on capacitor 23 will be negligible. . . . Thus, the
inclusion of capacitor 22, while not absolutely
necessary, improves the accuracy of the integrator
stage by minimizing the effect of leakage currents on
integration capacitor 23.
Gregorian, column 6, lines 8-30.
The examiner's position is that it would have been obvious to
incorporate Gregorian's capacitor 22 in the admitted prior art
circuit shown in Appellants' Figure 1 "for the purpose of
minimizing the effect of leakage current in the first impedance
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