Appeal No. 2000-2228 Page 2
Application No. 09/067,153
Because most self-timed circuitry is dynamic, explain the appellants, it is prone
to errors from noise. (Spec. at 4.) Furthermore, routing a clocking signal to each
dynamic circuit increases design complexity and clock loading. (Id. at 5.) Static
circuits, in contrast, do not suffer from many drawbacks of dynamic circuits. Given
enough time, static circuits can recover from an incorrect evaluation; a correct state can
be gained by waiting. Furthermore, static circuits require no clock signals, which
reduces design complexity and clock loading. (Id.) Dynamic circuits, however,
consistently outperform static circuits in terms of delay. (Id. at 6.)
Although static and dynamic circuits can be swapped for one another without
concern in a typical clocked system, the appellants assert that the use of static circuits
is not as simple in a self-timed system. (Id.) They explain that interlocking created by
using dynamic circuits in a self-timed system is lost when those circuits are replaced
with static circuits. (Id. at 6-7.)
The appellants’ add that their invention permits static circuits to be used in a
self-timed system, thereby attaining the benefits of static logic. (Id. at 8.) More
specifically, Figure 3 of their specification shows a self-timed logic circuit 300 featuring
a first transparent latch register 301 to receive one or more input data signals from one
or more sources. A control circuit 304 receives one or more valid signals corresponding
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Last modified: November 3, 2007