Appeal No. 2000-2228 Page 4
Application No. 09/067,153
OPINION
Rather than reiterate the positions of the examiner or appellants in toto, we
address the main point of contention therebetween. The examiner asserts, "Durham
teaches DATA signals which are evaluated by Self Resetting domino logic (SR) circuits
and clocked through a series of SR circuits along with an AND circuit (see Fig. 4)."
(Examiner's Answer at 5.) The appellants argue, "Durham teaches that SR circuits 402
produce a DATA OUT signal and not merely ‘clocked-through’ DATA signals." (Reply
Br. at 4.) The examiner responds, “[t]here is no basis to appellant's argument that claim
1 specifically and clearly recites the these DATA signals are directly connected to the
AND circuit without any evaluation or modification from the first transparent latch
register.” (Examiner’s Answer at 5.)
“Analysis begins with a key legal question -- what is the invention claimed?”
Panduit Corp. v. Dennison Mfg. Co., 810 F.2d 1561, 1567, 1 USPQ2d 1593, 1597 (Fed.
Cir. 1987). Here, independent claim 1 specifies in pertinent part the following
limitations: "the control circuit clocks the one or more input data signals from the first
transparent latch register to the combinatorial static logic block. . . ." Accordingly, the
claim requires that a control circuit cause data to be transferred from a transparent latch
register to a combinatorial static logic block without the data being modified.
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