Appeal No. 2000-2228 Page 6
Application No. 09/067,153
circuits 402, which comprise a plurality of domino logic rows (see, Figs. 5A and 5B) do
not merely pass through the received DATA signals from register 401, but perform
domino logic operations on those DATA signals so that they are not the same DATA
signals when outputted as DATA_OUT.” (Appeal Br. at 5.) The reference supports
their avowal by two implications. First, an explanation that “[m]acro 402 receives the
incoming data and produces output data that is transmitted to . . . AND circuit 404,”
col. 3, ll. 56-58 (emphasis added), implies that the macro modifies the incoming data.
Second, a labeling of the incoming data, viz., “INPUT1, INPUT2, and INPUT3,” Fig. 5A,
differently from the output data, viz., “DATA_OUT,” Fig. 5B, implies the same.
The examiner’s failure to show a control circuit that causes data to be transferred
from a transparent latch register to a combinatorial static logic block without the data
being modified negates anticipation. Therefore, we reverse the rejection of claim 1 and
of claims 2, 3, 5, and 9, which depend therefrom.
CONCLUSION
In summary, the rejection of claims 1-3, 5, and 9 under § 102(b) is reversed.
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