Appeal No. 2000-2228 Page 3
Application No. 09/067,153
to each of the input data signals. Combinatorial static logic 302 then receives the input
data signals from the first register and performs at least one function on the input data
signals. A second transparent latch register 303 receives the output from the
combinatorial static logic block, and the control circuit clocks the output data signals
through the second register to at least one sink.
A further understanding of the invention can be achieved by reading the following
claim:
1. A self-timed logic circuit comprising:
a first transparent latch register operable for receiving one or more
input data signals from one or more sources;
a control circuit operable for receiving one or more valid signals,
wherein each one of the one or more valid signals is associated with a
particular input data signal;
a combinatorial static logic block comprising one or more static
logic circuits, wherein the control circuit clocks the one or more input data
signals from the first transparent latch register to the combinatorial static
logic block when all of the one or more valid signals are received by the
control circuit, wherein the combinatorial static logic block produces one or
more output data signals; and
a second transparent latch register operable for receiving the one
or more output data signals.
Claims 1-3, 5, and 9 stand rejected under 35 U.S.C. § 102(b) as anticipated by
U.S. Patent No. 5,565,798 (“Durham”).
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Last modified: November 3, 2007