Appeal No. 2001-0184
Application No. 09/002,173
calculates an N bit sum from an N bit augend and an N bit addend
wherein a first circuit speculatively calculates bit N-1 of the
sum based only on bit N-1 of the augend, bit N-1 of the addend,
and a limited carry bit. The adder also comprises a second
circuit for calculating the limited carry bit based only on K
bits of the augend and K bits of the addend, where K is less than
N-1. A third circuit detects a potential difference between the
limited carry bit and an unlimited carry bit.
Representative independent claim 1 is reproduced as follows:
1. An adder having an adder width N, for calculating an N
bit sum S from an N bit augend A and an N bit addend B, said
adder comprising:
a first circuit for speculatively calculating bit SN-1 based
only on bit AN-1, bit BN-1, and a limited carry bit;
a second circuit for calculating said limited carry bit
based only on K bits of said augend and K bits of said addend,
wherein K is less than N-1;and
a third circuit for detecting a potential difference between
said limited carry bit and an unlimited carry bit
wherein the adder latency is related to the number of bits,
K, in the second circuit;
so that the adder latency is independent of the adder width
N.
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