Appeal No. 2001-0184
Application No. 09/002,173
322, 332, 336 and 340 of Figure 2 in the last bit slice block
400) for speculatively calculating bit SN-1 (output of gate 340 of
block 400) based only on bit SXN-1, SYN-1 and a limited carry bit,
presuming that the carry in the arithmetic circuit 224 would be
1; a second circuit (providing the limit carry to gates 332 and
336) for calculating the limited carry bit based only on the next
lower K bits of the addend and K bits of the augend; and a third
circuit (113 in block 300) for detecting a potential difference
between the limited carry bit and an unlimited carry bit, as
claimed.
The examiner contends that the latency of the adder 1 for
generating the speculative sum (the output of arithmetic circuits
121-124) is clearly related to the number of K bits in each block
(Figure 2), but it is independent of the number of bits of the
adder because the adder blocks have the same structure and the
speculative sum bits generated in each block is clearly
independent of the other block.
Appellant’s position is that Tomoji “always applies a
suspense carry bit to the arithmetic circuit 12j, ‘regardless of
the generator of the carry bit C1 in the carry lookahead
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