Appeal No. 2001-0184
Application No. 09/002,173
circuit’” [brief-page 4]. Thus, appellant contends that the
arithmetic circuit 12j calculates the sum assuming there is no
carry, then the correction circuit 14j corrects the calculated
sum if there is a carry so that Tomoji produces a tentative
result that is corrected if there is no carry bit.
Appellant argues that Tomoji does not speculatively
calculate the bits N-K above a number K so that the adder latency
is independent of the adder width. Thus, concludes appellant,
the latency of the arithmetic circuit 12j is dependent on the
arithmetic circuit width, which is the number of bits added by
the arithmetic circuit 12j. “Tomiji [sic, Tomoji] does not
disclose an adder with a latency that is independent of adder
width” [brief-page 5].
While the examiner agrees that the instant disclosed
invention differs from that of Tomoji in the feature that the
limited carry bit for each bitslice is generated, in the instant
invention, based only on the same number of K preceding bits, it
is the examiner’s position that this feature is not recited in
the instant claims and that the claims only require that the
limited carry bit for the most significant bit N-1 is calculated
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