Appeal No. 2000-1057
Application 09/016,100
Claim 17 is representative of the subject matter on
appeal and is reproduced below:1
17. A method for fabricating an integrated circuit,
comprising the steps of:
forming a conductive layer over a semiconductor body;
forming a patterned hardmask over said conductive
layer;
depositing a layer of refractory metal over said
patterned hardmask and said conductive layer;
reacting a portion of said refractory metal layer with
said conductive layer to form a silicide at a surface of said
conductive layer except under said patterned hardmask;
removing an unreacted portion of said refractory metal
layer;
removing said patterned hardmask;
selectively etching said conductive layer using said
silicide as a mask.
The references relied upon by the examiner are:
Grewal 5,591,301 Jan. 7, 1997
Hayashi et al. (Hayashi) 5,576,244 Nov. 19, 1996
GROUND OF REJECTION
Claims 17-23 stand rejected under 35 U.S.C. § 103 as
unpatentable over Grewal in view of Hayashi.
We reverse.
1 Claim 23, the only other independent claim, differs from
claim 17 in specifying a “reverse” patterned hardmask.
2
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