Appeal No. 2001-0607
Application No. 09/244,429
substrate is formed with a floating gate electrode, a control
gate arrangement and a dielectric spacer therebetween. It is
alleged that the conventional practice is to employ two different
etching stages due to the inability to achieve high selectivity
to polysilicon when etching the silicide. This has
conventionally been compensated for by providing an undesirably
thick polysilicon layer. The instant invention solves the
problem and allows a reduction in the thickness of the
silicide/polysilicon stack to no greater than about 800 Angstroms
by the use of an etching recipe comprising chlorine and oxygen
which enables the silicide and silicon layers to be etched in a
single etching step with high selectivity to the underlying oxide
thereby avoiding oxide damage.
Independent claim 18 is reproduced as follows:
18. A semiconductor device, comprising:
a semiconductor substrate;
an insulating layer over the semiconductor substrate;
a floating gate electrode overlying the insulating layer;
a dielectric layer substantially free of pitting therein
overlying the floating gate electrode; and
a control gate arrangement directly overlying the dielectric
layer wherein the control gate arrangement comprises a plurality
-2–
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