Appeal No. 2001-0836
Application No. 08/991,448
layer. Each stack further includes at least one sidewall layer,
with the HSG layer overlapping and contacting the sidewall layer.
According to Appellant (specification, pages 2-4), the inclusion
of the relatively large grain size HSG layer improves gate
coupling, while the relatively small grain size of the
polysilicon layer establishes a relatively flat surface interface
with the tunnel oxide layer.
Claim 9 is illustrative of the invention and reads as
follows:
9. A flash memory wafer, comprising:
a core memory region including at least one silicon
substrate; and
plural stacks in the core memory region, each stack
having at least one respective polysilicon layer on a tunnel
oxide layer and at least one HSG layer above the polysilicon
[sic, layer] each stack also having at least one sidewall
layer, the HSG layer overlapping and contacting the sidewall
layer.1
The Examiner relies on the following prior art:
Esquivel et al. (Esquivel) 4,855,800 Aug. 08, 1989
Yew et al. (Yew) 5,753,559 May 19, 1998
(filed Oct. 09, 1996)
Lim 5,879,989 Mar. 09, 1999
(filed Jan. 03, 1997)
1Both Appellant and the Examiner should note that the word
“layer” is missing after “polysilicon,” second occurrence, at
line 4 of claim 9 as it appears in the amendment filed November
18, 1999, Paper No. 9.
2
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007