Appeal No. 2001-1662
Application No. 09/048,208
Ground of Rejection
Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Abraham.
We Reverse
Background
In the manufacture of integrated circuits using a metal
etching method, metal lines are formed by depositing a barrier
layer over an oxide layer, followed by deposition of a metal
layer. Specification, page 1. The middle layer is then etched
away in those areas where it is not covered by a mask. Id.
Thereafter, the barrier layer is etched followed by an oxide
etcher over etched. Id.
A common problem which occurs in this conventional method is
that of microloading. Id. Microloading refers to the situation
where an etch rate is slower in areas where there is a high
density of line spacings as compared with the etch rate in less
dense areas. Abraham, column 2, lines 24-28. Microloading may
result in one or more of severe resist loss, poor wafer
planarization and metal shorts at narrow gap regions.
Specification, page 1.
According to the inventors, they have developed a multi-step
etch process having a particular sequence of etching steps which
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