Appeal No. 2001-2037
Application No. 08/884,912
The invention is directed to a method for reducing silicide
encroachment in a semiconductor device.
Representative independent claim 8 is reproduced as follows:
8. The method of forming an MOS transistor comprising the
steps of:
forming a gate electrode on a gate dielectric layer formed
on a first surface of a substrate;
forming an isolation region having a top surface extending
less than 1500Å above said first substrate surface;
forming a pair of recesses on opposite sides of said gate
electrode, said recesses extending beneath said first surface,
and
forming a silicide layer in said pair of recesses wherein
said silicide layer has a top surface with a height less than the
top surface of said isolation region.
The examiner relies on the following references:
Young et al. (Young) 4,851,257 Jul. 25, 1989
Subbanna 5,338,698 Aug. 16, 1994
Song 5,686,331 Nov. 11, 1997
(filed Dec. 24, 1996)
Venkatesan et al. (Venkatesan) 5,736,435 Apr. 7, 1998
(filed Jul. 3, 1995)
Claims 8, 9 and 24 stand rejected under 35 U.S.C. 102(b) as
anticipated by Subbanna.
Claims 10, 12, 13, 15, 16 and 18-22 stand rejected under
-2–
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