Ex parte GAMBINO et al. - Page 2


          Appeal No. 1999-2115                                                        
          Application No. 08/724,574                                                  


          14), and an integrated circuit chip (claims 15-20).  In                     
          particular, the scratches formed during a chemical mechanical               
          polish (CMP) process are removed by heating the dielectric layer            
          to a temperature high enough to cause the dielectric layer to               
          reflow, thereby filling in the scratches and providing a smooth,            
          planar surface for subsequent processing steps.  (Appeal brief,             
          page 2.)  Further details of this appealed subject matter are               
          recited in illustrative claims 1 and 9, the sole independent                
          claims on appeal:                                                           
                    1.  A method for removing scratches from a                        
               dielectric layer comprising the steps of:                              
                    providing a layer of a reflowable dielectric                      
               material;                                                              
                    subjecting the layer to a chemical mechanical                     
               polish; and                                                            
                    removing scratches formed during the chemical                     
               mechanical polish by heating the layer of the                          
               reflowable dielectric material to a temperature                        
               sufficient to cause the reflowable dielectric material                 
               to reflow.                                                             
                    9.  A method for manufacturing an integrated                      
               circuit chip comprising the steps of:                                  
                    providing a substrate;                                            
                    depositing a layer of a reflowable dielectric                     
               material on a surface of the substrate;                                
                    defining a pattern in the layer of the reflowable                 
               dielectric material, thereby forming a patterned                       
               substrate;                                                             
                    non-selectively depositing a conductive layer                     
               over a surface of the patterned substrate;                             
                    chemical mechanical polishing the conductive                      
               layer to the surface of the patterned substrate; and                   



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