Appeal No. 1999-2115
Application No. 08/724,574
in selected areas (e.g., areas that tend to be dished after the
conventional CMP process) so that the polishing rate in these
areas is altered (e.g., by modifying the area through a plasma
nitridation process to create a material more resistant to
polishing, thereby decreasing the polishing rate so that the
dishing is eliminated). (Column 2, line 63 to column 3, line
4.) Alternatively, where large height differences exist in the
surface to be planarized, Yu '843 teaches modifying the higher
area through an ion implantation process to create a material
less resistant to polishing, thereby increasing the polishing
rate so that the overall surface is flat. (Column 3, lines 4-
10.)
The examiner admits that Yu '843 does not teach the step of
removing scratches formed on a dielectric layer during the CMP
step, as recited in independent claim 1 on appeal. (Examiner's
answer, page 7.) In an attempt to account for this difference,
the examiner relies on the teachings of Rao. According to the
examiner, Rao "teach[es] reflowing boron and phosphorus doped
glass during integrated circuit chip manufacture...and teaches
the benefits of the glass reflowing step." (Id.) The examiner
then concludes that "[i]t would have been obvious to...reflow
the glass of Yu..." and that "[o]ne of ordinary skill in this
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