Appeal No. 1999-2691
Application No. 08/590,348
circuit 132 and an A/D converter 135 as claimed. According to the
examiner (answer, page 4), the “pulse Gen. for A/D 138 can prevent
the A/D converter 135 from inputting the analog signals at the same
time that the analog signal changes it[s] value, see col. 7 and 8,
lines 1-68, Figs. 13-17).” Appellant argues (brief, page 9) that:
[B]ecause the pulse generators receive the same system
clock from frequency generator f, the pulses produced by
generators 137 and 138 will be in phase, and will have
frequencies that are certain multiples of each other.
Over time, therefore, there inevitably will occur a point
at which the A/D clock pulse is produced at the same time
that an analog image signal value is sampled and latched
by the sample/hold circuits. Contrary to the assertion
in the final Office action, Fig. 15B in fact shows an
example of such simultaneous occurrence of signal SMPC
(7) and A/D CLK R (17), as well as simultaneous
occurrence of SMPY signal (9) and A/D CLK B, G (16).
Further, it is emphasized that the timing waveforms of
Figs. 15B and 17 represent only a finite sample of the
clock pulse trains, which continue to be produced during
operation of the apparatus for an extended period of time
during image scanning.
In response to appellant’s arguments, the examiner directs
appellant’s attention to “Figs. [sic, Fig.] 15B, signal SMPG (8)
and A/D CLK B, G (16) and Fig. 15A” (answer, page 7). According to
the examiner, “when the SMPG signal level is High (on) (i.e., the
analog signal changes its value), the A/D CLK B, G signal level is
Low (off) at that time, therefore, the A/D converter is inherently
preventing [sic, prevented] from inputting an analog signal during
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