Appeal No. 1999-2691
Application No. 08/590,348
its Low signal level where the SMPG signal changes its value (i.e.,
High) at that time.”
We agree with appellant that the noted overlapping times are
instances in which Hasegawa does not perform the function of
“preventing said A/D converter from inputting said analog signal at
the same time that said analog signal changes its value.” On the
other hand, we agree with the examiner that during the time period
when “signal SMPG (8) and A/D CLK B, G (16)” do not overlap,
Hasegawa has a “means for preventing said A/D converter from
inputting said analog signal at the same time that said analog
signal changes its value.” Inasmuch as nothing in claim 7 on
appeal precludes Hasegawa ‘690 from having a “means for preventing”
the A/D converter from inputting analog signals at a specified time
as well as a means for allowing the A/D converter to input analog
signals at a specified time, we find that claim 7 reads entirely on
the noted limited time period in Hasegawa ‘690 for “preventing said
A/D converter from inputting said analog signal at the same time
that said analog signal changes its value.” Thus, the 35 U.S.C.
§ 102(b) rejection of claim 7 is sustained.
Turning next to the 35 U.S.C. § 103(a) rejection of claim 4,
appellant and the examiner both agree (brief, pages 10 and 11;
answer, page 5) that Hirota does not disclose a timing generator
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