Ex Parte ROY - Page 7




          Appeal No. 2001-2388                                                        
          Application 09/151,948                                                      


          evidence or technical reasoning which shows that Huang’s                    
          structure and that of the appellant’s admitted prior art are                
          equivalent.                                                                 
               The examiner argues that it would have been obvious to one             
          of ordinary skill in the art to use Huang’s dual damascene method           
          instead of the appellant’s admitted prior art method for making a           
          liquid crystal display integrated circuit device because Huang              
          teaches that an etch back method (which appears to be the method            
          used to form the metal pixels in the appellant’s admitted prior             
          art structure) has the disadvantage of residual metal shorts                
          leading to inconsistent manufacturability, low yields, uncertain            
          reliability, and poor ultra large scale extendability (answer,              
          pages 10-11).  Huang’s disclosed disadvantage of an etch back               
          method relied upon by the examiner, and the additional disclosed            
          disadvantages set forth above in the discussion of Huang, are in            
          the context of ultra large scale integration semiconductor wiring           
          having planarized layers with minimum spacing between wiring                
          lines (col. 1, lines 17-20).  The examiner has not established              
          that one of ordinary skill in the art would have considered these           
          disadvantages to exist in the appellant’s admitted prior art                
          liquid crystal display integrated circuit device having metal               
          pixels instead of minimum-spaced conductive wiring and having on            

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