Appeal No. 2001-2610
Application No. 09/052,247
With regard to independent claim 27, the examiner asserts
that Mahalingaiah teaches, at column 7, lines 63-65, that the
start and end predecode bits indicate the boundaries of the
prefetched instruction, therefore designating the range of
desired data values to be accessed, meeting the language of claim
27 which requires that prefetching is done in response to the
predecode bits, and not in response to the predecode bits having
a preselected value [answer-page 9].
It is appellants’ position that Mahalingaiah does not
disclose predecode bits, which, in response thereto, a next
sequential instruction set is prefetched into an instruction
storage device.
We have carefully reviewed the evidence before us,
including, inter alia, the arguments of appellants and the
examiner, and we conclude that, to whatever extent the examiner
has set forth a prima facie case of anticipation, appellants have
made arguments that raise serious doubts about Mahalingaiah
anticipating the instant claimed subject matter. Accordingly, we
will not sustain the rejection of claims 1 and 27, or of claims
8-13 and 33, dependent therefrom, under 35 U.S.C. 102(e).
Turning, first, to independent claim 1, we note, initially,
that we find the double negative language, “if no remaining
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