Appeal No. 2002-1594
Application No. 09/057,573
We thus agree with appellants that a case for prima facie obviousness of the
subject matter as a whole of claim 1 has not been established. We do not sustain the
rejection of claim 1, nor of claims 2 or 3 depending therefrom.
In response to the rejection of claim 7, appellants argue that Kawashima does
not disclose or suggest the jitter feedback slicer responding to the phase error signals
to one of increase or decrease the voltage of the analog input signal to compensate for
change in the signal/slice level from the jitter feedback signal. (Brief at 6.) The
examiner responds that, as depicted in Figure 2 or 4 of Kawashima “the error signal c is
sent to a summing amplifier 4 [sic; 24]” where it is summed with the input from the
buffer amplifiers, meeting “at least one of” an increase or decrease of the analog input
signal as claimed. (Answer at 5.)
Figure 2 of Kawashima is a circuit diagram of an embodiment of a slice level
generating section wherein peak detection and bottom detection section 30 and slice
level generating section 32 (Fig. 1) are combined. Col. 7, ll. 1-6. Summing amplifier 24
receives on one input the output of buffer amplifier 23 and on the other input error
signal C from phase comparator 15, thus summing the signals and generating slice
level B. Col. 7, ll. 26-33.
We agree with the examiner that Kawashima teaches the limitations of claim 7
that appellants argue in the Brief as being absent from the reference. Counsel for
appellants agreed with the examiner’s assessment, thus conceding the point, at the oral
hearing. We do not find the argument in the Brief persuasive of nonobviousness.
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