Appeal No. 2003-0623
Application No. 09/348,632
1. A process for fabricating an interconnect structure on an electronic device with void-free
seamless submicron conductors comprising the steps of:
forming an insulating material on a substrate,
lithographically defining and forming recesses for submicron lines and/or submicron vias in
said insulating material in which interconnection conductor material will be deposited,
forming a conductive layer on said insulating material serving as a plating base,
depositing by a damascene process said conductor material in a seamless and void-free
manner by electroplating from a bath containing additives, said bath additives causing the plating
rate to increase with depth along the sidewall of a recess, thereby preventing the formation of a
seam or void in a conductor in said recesses, and said conductor material comprising coper and
planarizing the resulting structure to accomplish electrical isolation of individual seamless
and void-free lines and/or seamless and void-free vias.
115. The process of claim 2 wherein the copper is deposited in a double damascene structure.
The prior art references relied upon by the examiner are:
Aigo 4,339,319 Jul. 13, 1982
Poris 5,256,274 Oct. 26, 1993
Chang et al. (Chang) 5,266,446 Nov. 30, 1993
Gelatos et al. (Gelatos) 5,391,517 Feb. 21, 1995
Jain 5,602,423 Feb. 11, 1997
Huang et al. (Huang) 5,635,423 Jun. 3, 1997
Lowenheim, Electroplating, McGraw-Hill Book Co., pp. 198-202 (1978).
Silman et al. (Silman), Protective and Decorative Coating for Metals, Finishing Publications
LTD., pp. 310-314 (1978).
The references relied upon by the appellants are:
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