Appeal No. 2002-2086
Application 09/010,396
BACKGROUND
The invention relates to calculation of the interconnect
delay between the driver and one of the sinks on a net in an
integrated circuit.
Claim 1 is reproduced below.
1. A method for placement of a plurality of cells on a
surface of an integrated circuit, said method comprising the
steps of:
calculating an interconnect delay, defined as a delay
for an interconnect between a driver and a sink in a
placement of cells;
comparing the placement of cells to predetermined cost
criteria which include a timing criterion based upon the
interconnect delay; and
moving cells in the placement of cells to alternate
locations on the surface if necessary to satisfy the
predetermined cost criteria,
wherein the interconnect is part of a net, and wherein
calculation of the interconnect delay comprises determining
a first delay that accounts for a contribution of a direct
path between the driver and the sink and determining a
second delay that accounts for a contribution of a portion
of the net that does not include the direct path to the
interconnect delay.
The examiner relies on the following reference:
Li et al. (Li) 5,666,290 September 9, 1997
Claims 1, 6-8, 12, 18, and 22-26 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Li.
We refer to the final rejection (Paper No. 13) (pages
referred to as "FR__") and the examiner's answer (Paper No. 19)
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