Appeal No. 2002-2086
Application 09/010,396
modeling the interconnect comprises utilizing a term that
corresponds to a length of an overlapping wire" (claim 23),
distinguish over the delay expression Di = 3 RkiCk (summation over
all k) in van Ginneken and TDi = 3 RkiCk (summation over all k) in
Gupta (cited above). The expansion of each of these summations
can be partitioned into one term representing delay from a direct
path and a second summation representing a delay which accounts
for a contribution of the net that does not include the direct
path, e.g., using Gupta:
Di = DLINKi + DTPLGi = RiiCk + 3 RkiCk
k…i
Where Di, DLINKi, and DTPLGi correspond to )INTi, )LINKi, and )TPLGi,
respectively, in equations (7)-(9) on page 8 of appellants'
specification, except that there is no unit length capacitance c0
and the resistance is a lump resistance Rki rather than a
function of length r0loji. Since no equation or model (e.g., a
unit length capacitance) is claimed, the limitations of first and
second delays do not appear to distinguish over the delay
expressions in these two references. Both expressions also
involve overlapping wires as recited in claim 23.
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