Appeal No. 2002-2330
Application No. 09/116,260 Page 2
derived from a reading of exemplary claim 36, which is reproduced
as follows:
36. A microprocessor comprising:
an instruction decoder receiving a delayed instruction from
a memory, for decoding the delayed instruction to output a
control signal, said delayed instruction including a field for
specifying a delay value;
a program counter for calculating and outputting an address
value designating a location of the memory at which an
instruction to be processed is stored to control a program
sequence; and
an instruction execution unit performing an operation
specified by the delayed instruction based on the control signal
in a case of a coincidence between a value of said program
counter and a first program counter value which is specified by
the field of the delayed instruction as the delay value.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Morrison et al. 4,847,755 Jul. 11, 1989
(Morrison)
Hagqvist et al. 5,581,776 Dec. 3, 1996
(Hagqvist)
Claims 36, 37 and 39-42 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Hagqvist in view of Morrison.
Rather than reiterate the conflicting viewpoints advanced by the
examiner and appellants regarding the above-noted rejection, we
make reference to the examiner's answer (Paper No. 36, mailed May
20, 2002) for the examiner's complete reasoning in support of the
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