Appeal No. 2002-2330
Application No. 09/116,260 Page 6
teachings.” It is argued (brief, page 8) that Hagqvist merely
discloses a CPU which is fed address values, and that “nothing in
Hagqvist et al. shows, teaches or suggests a delayed instruction
includes a field for specifying a delay value and a first program
counter value is specified by the field of the delayed
instruction as the delay value as claimed in claim 36.” It is
further argued (brief, page 10) that Morrison merely discloses
totally coupling each processor element to a register during its
particular instruction firing time such that the instruction
firing time indicates the instruction execution timing.
Appellants assert (id.) that nothing in Morrison shows, teaches
or suggests that the registers are for holding the value to be
compared with the program counter, and (brief, page 11) that
“Morrison et al. does not show, teach or suggest a delayed
instruction, decoding a delayed instruction or determining a
coincidence between a value of a program counter and a first
program counter value specified by the field of a delay
instruction as a delay value as claimed in claim 36.”
From our review of Hagqvist and Morrison we find that
Hagqvist is directed to a system for enabling a microprocessor to
efficiently branch to an alternate program source when a portion
of the program is superseded (col. 1, lines 8-10). As shown in
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