Appeal No. 2002-2330
Application No. 09/116,260 Page 7
the figure, CPU 10 will normally access addresses 1-200 from
operating program 15 and executes them in serial fashion. Each
time an address is accessed, program counter 28 is incremented to
a next value. Assume that addresses 101-125 in ROM 14 have been
replaced by addresses 301-325 in auxiliary storage module 20.
When program counter 28 manifests a value 101, that value is
determined by address comparator 22 to match a prestored value of
101. As a result, comparator 22 issues a control signal to
program counter load controller 26 which causes a program count
of 301 to be written from branch control register 24 into program
counter 28. CPU 10 then responds to program count 301 by
accessing, via I/O module 18, address 301 in auxiliary storage
module 20. When program counter 28 reaches address 325, that
value is passed to comparator 22 into which value 325 has been
has been previously loaded. Upon determining a match, address
comparator 22 issues a signal to program counter load control 26
which causes a program count of 126 to be loaded from branch
register 24 into program counter 28. When CPU next accesses
program counter 28, address value 126 is outputted into line 30.
CPU 10 thus accesses address 126 in operating program 15 in ROM
14. The program then continues down the remaining addresses in
operating program 15 until its termination (col. 3, lines 23-51).
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Last modified: November 3, 2007