Appeal No. 2003-1281
Application No. 08/991,232
Claims 1, 9 and 21 stand rejected under 35 U.S.C. § 102(e)
as being anticipated by Zavracky.
Claims 2 through 8 and 10 through 20 stand rejected under 35
U.S.C. § 103(a) as being unpatentable over Zavracky in view of
Narasimhan.
Reference is made to the briefs (paper numbers 33 and 35)
and the answer (paper number 34) for the respective positions of
the appellant and the examiner.
OPINION
We have carefully considered the entire record before us,
and we will sustain the anticipation rejection of claim 9,
reverse the anticipation rejection of claims 1 and 21 and reverse
the obviousness rejection of claims 2 through 8 and 10 through
20.
Turning first to the anticipation rejection of claims 1, 9
and 21, Zavracky discloses a programmable logic circuit 802, a
microcontroller 804 and 806, and a memory array 808 stacked on a
single integrated circuit chip 800 (Figure 13; column 12, lines
29 through 39).
Appellant argues throughout the briefs that the circuit
structure in Zavracky is neither “fabricated as a single
integrated circuit chip” (claims 1 and 21) nor “fabricated on a
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