Appeal No. 2003-1281
Application No. 08/991,232
F.3d 1043, 1047, 34 USPQ2d 1565, 1567 (Fed. Cir. 1995).
Claim 9 differs from claims 1 and 21 because it merely
requires that all of the circuit structure be “fabricated on a
single integrated circuit chip.” When claim 9 is given its
broadest reasonable interpretation, we find that the vertical
circuit structure disclosed by Zavracky (Figure 13) is indeed
“fabricated on a single integrated circuit chip.” During
examination proceedings, a claim is given its broadest reasonable
interpretation consistent with the specification. In re Morris,
127 F.3d 1048, 1054, 44 USPQ2d 1023, 1028 (Fed. Cir. 1997).
Nothing in the disclosed and claimed invention precludes
fabrication in a vertical direction on the single integrated
circuit chip disclosed by Zavracky. Accordingly, the
anticipation rejection of claim 9 is sustained.
Turning to the obviousness rejection of claims 2 through 8
and 10 through 20, we find that the examiner’s reasoning (answer,
pages 5 and 6) for combining the two references is not based upon
the evidence of record. An obviousness rejection can not be
based upon unsupported conclusory statements made by the
examiner. In re Lee, 277 F.3d 1338, 1345, 61 USPQ2d 1430, 1435
(Fed. Cir. 2002). Even if we assume for the sake of argument
that it would have been obvious to one of ordinary skill in the
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