Appeal No. 2003-1383
Application No. 09/451,414
along with the examiner’s rationale in support of the rejection and arguments in rebuttal
set forth in the examiner’s answer.
With full consideration being given to the subject matter on appeal, the
examiner’s rejections and the arguments of appellant and examiner, for the reasons
stated infra, we reverse the examiner’s rejection of claims 1 and 2 under 35 U.S.C.
§ 103.
Appellant argues on page 5 of the Brief that:
[A] combination of applicant’s admitted prior art (showing two separate
phase locked loops) and Katoh (showing two separate phase locked
loops) does not teach or suggest one phased locked loop, generating a
read clock when reading and a write clock when writing, as specified in
claim 1.
The examiner asserts on page 4 of the answer that Katoh discloses that “a single
channel is processing both the channel data and pseudo channel data to produce a
clock signal at a single output RCK.” Further, the examiner asserts that both Katoh and
AAPA are concerned with reading and writing data to a disk drive. Finally, the examiner
concludes that given the two prior art teachings it would be obvious to apply the dual
input to a single PLL teaching of Katoh to the AAPA “thereby providing a read/write
clock output responsive to the data and wobble signal of AAPA because it would have
provided the mechanism to speed up the processing of the data.”
We disagree with the examiner’s reasoning. An obviousness analysis
commences with a review and consideration of all the pertinent evidence and
arguments. “In reviewing the examiner’s decision on appeal, the Board must
necessarily weigh all of the evidence and argument.” In re Oetiker, 977 F.2d 1443,
-3-
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