Appeal No. 2003-1383
Application No. 09/451,414
1445, 24 USPQ2d 1443, 1444 (Fed. Cir. 1992). “[T]he Board must not only assure that
the requisite findings are made, based on evidence of record, but must also explain the
reasoning by which the findings are deemed to support the agency’s conclusion.” In re
Lee, 277 F.3d 1338, 1344, 61 USPQ2d 1430, 1434 (Fed. Cir. 2002). In addition, our
reviewing court stated in In re Lee, 277 F.3d at 1343, 61 USPQ2d at 1433, that when
making an obviousness rejection based on combination, “there must be some
motivation, suggestion, or teaching of the desirability of making the specific combination
that was made by applicant” (quoting In re Dance, 160 F.3d 1339, 1343, 48 USPQ2d
1635, 1637 (Fed. Cir. 1998)).
Claim 1 includes the limitation of “the phased locked loop generating a read clock
signal when the drive is reading data, and the phase locked loop generating a write
clock signal when the drive is writing data.” Thus, the scope of independent claim 1 is
that one Phase Locked Loop (PLL) generates both the read and write clock.
We find that both the AAPA and Katoh, teach systems where the write clock is
generated by a separate PLL than the read clock. See, for example, figures 1 and 3 of
Katoh, read clock signal RCK is generated by “Channel PLL” and write clock signal
WCK is generated by “Wobble PLL.”2 We concur with the examiner that Katoh teaches
“Channel PLL,” which generated clock RCK, has input from either one of two sources
(see column 7, lines 30-24). However, we find that this teaching is limited to the read
clock, RCK, as Katoh explicitly teaches that the write clock is generated by a separate
PLL than the read clock. Thus, we do not find that Katoh suggests that the same PLL
2 Katoh teaches an embodiment of figure 3, which uses only one clock, RCK, however this embodiment
is described in column 13, line 46, for a read only device, and as such has no need for a write clock.
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