Appeal No. 2003-1965
Application 09/275,496
See page 1 of Appellant’s specification. There have been several
attempts to solve the problem of maintaining phase coherence
between the data transmitted from one ASIC to the same received
at another ASIC when each ASIC has its own clock domain. See
page 3 of Appellant’s specification. Appellant solves this
problem of ASIC-to-ASIC high speed data transmissions by
providing: a transmitter and receiver operating within the same
frequency and clock domain; a receiver that can sample data at n
phase intervals; a mechanism for synchronizing this data to a
common phase interval; a mechanism for analyzing the
synchronizing data and subsequently determining one of the n
phase intervals to be best fit and a mechanism for reconstructing
n data packages from synchronized data that represent n data
packets sampled at n phase intervals. See page 6 of Appellant’s
specification.
Referring to figure 1, an overall diagram of a high speed
serial interface 10 is shown. The system comprises a
transmitting ASIC 14, a receiving ASIC 16, and a reference clock
12 that drives both ASICs 14 and 16. See page 10 of Appellant’s
specification. Both transmitting ASIC 14 and the receiving ASIC
16 comprising PLL’s 18 and 24 that receive reference clock signal
12 and allow their respective ASIC devices to operate at some
2
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