Appeal No. 2003-1965
Application 09/275,496
common frequency, Px. Since both PLL’s 18 and 24 use the same
reference clock, their frequencies will be the same but not
necessarily in phase. The PLL’s 18 and 24 also each generate
additional clock signals that operate at a frequency of Bx. The
PLL 24 within the receiving ASIC 16 generates n Bx clocks, each
phased spaced within a Bx clock cycle as well as a receiver Px
clock that will ultimately return data to the receiver ASIC 16
logic. Within the receiving ASIC 16, a receiver 26 receives and
samples the data packet 22 at each of the n phase intervals in
the Bx frequency domain, and on both edges of each n phase
interval clocks. The samples 28 are synchronized to the Bx clock
having a phase interval of 0 degrees and are then stored in a
shift register 30 and analyzed to determine an initial phase
relationship between the transmitted data packets and the
receiver clock. If phase delay drifting has been detected, the
receiver can compensate for the phase delay drifting by re-
synchronizing the received data packets to the receiver clock
phase. See page 11 of Appellant’s specification.
The system also has a mechanism for storing a history of the
synchronized data, using the results of the comparison analysis
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Last modified: November 3, 2007