Appeal No. 2003-1965
Application 09/275,496
to determine transmitter to receiver phase delay drift, and a
mechanism for compensating for the identified phase delay drift.
See pages 6 and 7 of Appellant’s specification.
Referring to figures 4 through 6, a data packet collection
scheme pursuant to Appellant’s invention is depicted by utilizing
six Bx clocks and six data paths. In figure 4, a timing diagram
34 shows a single Px clock signal (system clock) and six Bx clock
signals identified as Bx0, Bx1, Bx2, Bx3, Bx4 and Bx5. As can be
seen, each Bx clock is phase shifted by a 30 degree interval
relative to the Bx0 clock signal. During operation, the data
stream is sampled by each of the Bx clocks. The resulting sample
is stored into the n=0 history buffer depicted in figure 5. At
the subsequent five Bx clock intervals, it can be seen that data
bit B is sampled. The results are stored in sequence history
buffers (n=1, 2, 3, 4, and 5) as shown in figure 5. See page 22
of Appellant’s specification. As can be seen in figures 4 and 5,
the history buffers 38 could be examined to determine which of
the n history buffers contain the BCDE signature. In this case,
buffers n=1, 2, 3, 4, and 5 each contain the signature data
packet. From those buffers that contain the signature, a middle
one of the buffers could be selected to identify the “preferred”
phase interval that represent the best fit among all of the six
4
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: November 3, 2007