Appeal No. 2003-2097
Application No. 09/247,926 Page 2
BACKGROUND
Appellant’s invention relates to a process for fabricating a
semiconductor integrated circuit device having a polycide line
and impurity region respectively exposed to contact holes that
are different in depth. An understanding of the invention can be
derived from a reading of exemplary claim 1, which is reproduced
as follows:
1. A process for fabricating a semiconductor device,
comprising the steps of:
a) preparing a semiconductor structure including a first
lower-level conductive line having a semiconductor layer and a
refractory metal silicide layer laminated on said semiconductor
layer and a second lower-level conductive line without a
refractory metal silicide layer;
b) forming an inter-level insulating layer over said
semiconductor structure having a first portion over said first
lower-level conductive line and a second portion over said second
lower-level conductive line;
c) etching said first portion and said second portion until
said refractory metal silicide layer of said first lower-level
conductive line is exposed to a first contact hole, said second
lower-level conductive line being still covered with a remaining
second portion;
d) removing a part of said refractory metal silicide layer
exposed to said first contact hole from said first lower-level
conductive line; and
e) etching said remaining second portion for exposing said
second lower-level conductive line to a second contact hole.
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