Appeal No. 2004-0633
Application No. 10/011,198
the brief, appellants state that Ito addresses a “stud up”
structures that extends upward from an interconnect. Appellants
state that in contrast, Yu focuses on how its metal-2 line must
extend downward toward the drain of Yu’s substrate. Appellants
state that Ito touts the benefits of a damascene process used to
form an interconnect. Appellants state that this is yet another
conflict with Yu. At the bottom of page 10 of the brief,
appellants state that Ito criticizes the non-damascene method of
forming wiring and a projection as resulting in different resist
layer thicknesses. At the top of page 11 of the brief,
appellants state that, to the contrary, it is a non-damascene
process that Yu proposes in forming its metal-2 line, a
component that is arguably analogous to Ito’s wiring.
On pages 4-5 of the answer, the examiner’s position is that
Ito basically sets forth the subject matter of claims 31-331,
except that Ito does not expressly teach using the multilayer
structure within a memory structure, which is a limitation of
claim 31. The examiner relies upon Yu for disclosing memory
cells of a random access memory that utilize multilayer wiring
to connect to underlying field effect transistors. Answer, page
4. Appellants also do not dispute the examiner’s findings with
regard to Yu (that Yu establishes that is generally known in the
art to use multilayer wirings in making electrical connections
to random access memory).
In view of the above, it is the examiner’s position that
the multilayer wiring structure of Ito is suitable for a random
access memory. Thus, the teachings relied upon by the examiner
do not involve interchanging one of the process steps of Ito
with one of the process steps of Yu, for example, such that the
1 Appellants do not dispute these findings made by the examiner.
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