Appeal No. 2004-0999
Application No. 09/997,086
prevention of defects, such as, cracks and delamination, from
forming and/or propagating in the interconnect layer of the
integrated circuitry of the microelectronic device wafer. See
Appellants' specification, page 1, lines 4-9. Appellants
disclose at least one trench in the interconnect layer of a
microelectronic device wafer such that at least one wall of
each trench will be positioned on either side of where a wafer
saw will cut through the microelectronic device wafer. See
Appellants' specification, page 6, lines 1-3.
Appellants' Fig. 1 illustrates a microelectronic device
wafer 100 similar to the prior art microelectronic device wafer
200 of Figs. 15 and 16 comprising a semiconductor wafer 114
mounted onto a sticky, flexible tape 116 and an interconnect
layer 108 disposed on the semiconductor wafer 114. The
interconnect layer 108 is generally alternating layers 112 of
dielectric material and patterned electrically conductive
material. See Appellants' specification, page 6, lines 4-15.
A plurality of dicing streets 104 separate the individual
integrated circuitry 102. Generally, the dicing streets 104
run perpendicularly to separate the integrated circuitry 102
into rows and columns. At least one guard ring 106 isolates
2
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