Appeal No. 2004-0999
Application No. 09/997,086
1. A method of dicing a microelectronic device wafer,
comprising:
providing a microelectronic device wafer comprising a
semiconductor wafer having an interconnect layer disposed
thereon, said microelectronic device including at least two
integrated circuits formed therein separated by at least one
dicing street;
forming at least one trench through said interconnect layer
within said at least one dicing street;
cutting through said semiconductor wafer within said at
least one dicing street. REFERENCES
The references relied on by the Examiner are as follows:
Mori 5,024,970 Jun. 18, 1991
Igarashi et al. 6,306,731 Oct. 23, 2001
(Igarashi) (filed Apr. 3, 2000)
Ibnabdeljalil et al. 6,365,958 Apr. 2, 2002
(Ibnabdeljalil) (filed Jan. 21, 1999)
Kroeninger et al. DE 198 40 508 A1 Dec. 2, 1999
(Kroeninger)
Stanley Wolf "Silicon Processing for the VSLI Era" Volume 1,
Lattice Press 1986, Chapter 16.
REJECTIONS AT ISSUE
Claims 1, 3, 5-9, 11, 13, and 14 stand rejected under
35 U.S.C. § 103 as being obvious over Ibnabdeljalil in view of
Mori. Claims 2 and 10 stand rejected under 35 U.S.C. § 103 as
being obvious over Ibnabdeljalil in view of Mori and further in
view of Kroeninger. Claims 4 and 12 stand rejected under
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