Appeal No. 2004-1543 Page 6
Application No. 09/303,991
a buffer 77 before being read into one of two memory arrays 82 or 84 in the
memory section 66. Memory addresses are assigned to each digital video datum
by address generator 80 in the timing section 64. Once digital delay generators
86 are properly adjusted the memory addresses are assigned only to digital
video data of interest, i.e. the digital video data corresponding to the horizontal
and vertical deadzones are not assigned memory addresses and consequently
are not read into either memory array 82 or 84. After an entire frame of digital
video data is stored in either memory array 82 or 84, the digital data is read out
of that memory array in the proper order so that this ordered digital video data is
either displayed using new global addresses and a digital display or is
digital-to-analog (D/A) converted resulting in a high-resolution analog video
signal. This high resolution analog video signal can be displayed as the
composite image 30 (without deadzones) using a high resolution TV monitor. The
multicamera device in FIG. 9 will now be described in more detail.
A video gen-lock circuit 70 synchronizes the arrival of the analog video
signals from the solid-state cameras 45 with respect to each corresponding
horizontal sync pulse. The synchronization of the gen-lock circuits 70 and pixel
clock 69 should ensure that the video signals on line 46 are synchronized.
However, if additional synchronization, a buffer circuit 73 in the buffer and clamp
circuit 72 could provide a delay mechanism for delaying the analog signal so that
the video lines from all four cameras arrive at the A/D converter 76, consistently
to within a fraction of one system pixel cycle. The buffer circuits would provide
variable delays and outputs synchronized with the pixel clock. The system pixel
clock 69 could be from one of the solid-state cameras 45 or an outside clock. The
gen-lock circuit 70 also provides horizontal sync pulse information to the digital
delay generator 86. The digital delay generator 86 then outputs delayed
horizontal and vertical sync pulses to the address generator 80, which tell the
address generator 80 when to begin generating memory addresses.
The buffer and clamp circuit 72 provides video voltage regulation so that
the A/D conversion of the analog video signal is on an absolute level. The portion
of the video line directly following the horizontal sync pulse must be clamped at a
fixed voltage level corresponding to black for example. This is necessary
because the A/D converter 76 in the A/D section 62 will eventually A/D convert
the video signal using this fixed voltage level as a reference level. Without the
buffer and clamp circuit 72 this reference voltage level will typically vary a few
millivolts from line to line and camera to camera. The buffer circuit 73 and clamp
circuit 74 in the buffer and clamp circuit 72 are standard buffer and clamp
circuits.
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