Appeal No. 2004-1543 Page 7
Application No. 09/303,991
The clamped and delayed video signal output from the buffer and clamp
circuit 72 as well as the synchronizing signals output by the video gen-lock circuit
70 are input to the A/D section 62. The A/D converter 76 samples the output of
the buffer and clamp circuit 72, N times where N corresponds to the number of
pixels in a horizontal scan of the solid-state sensor array 17; typically N is
somewhere in the range of 520 to 590. The analog voltage levels V1, V2, V3 . . .,
VN shown in FIG. 4d are all converted to digital signals, (typically 8 bits). In order
to obtain real time high resolution images the A/D converter 76 is preferably a
flash converter. The A/D conversion process is clocked at a rate corresponding
to the system pixel clock 69.
The digital video data output from the A/D converter 76 is then input to a
buffer 77 which holds that digital video data so that the address generator 80 can
feed address lines into memory arrays 82 and 84 according to the system pixel
clock 69 and/or the horizontal and vertical sync pulses. The other circuit in the
A/D section 62 is the digital delay generator 86. The digital delay generator 86 is
connected to the video gen-lock circuit 70 which provides the digital delay
generator 86 with horizontal and vertical sync pulse information. The digital delay
generator 86 has some type of discrete level setting mechanism such as a thumb
wheel switch. This thumb wheel switch can be used to delay the onset by the
address generator 80 of loading addresses into the memory arrays 82 or 84. This
delay actually can comprise two components. There can be a delay in terms of
horizontal sync pulses after a vertical sync pulse for eliminating horizontal
deadzones, and there can be a delay in terms of pixel clock pulses after a
horizontal sync pulse to eliminate vertical deadzones. In other words, although
the A/D converter 76 is continuously digitizing the video signal, the digitized video
signals output by the buffer 77 are ignored by the address generator 80 until it is
commanded to begin address generation and signal storage by the digital delay
generator 86. This will effectively eliminate any digital video data corresponding
to the horizontal and vertical deadzones and only digital video data without
deadzones is stored in the memory arrays 82 and 84. This operation is controlled
by observing the composite image on the high-resolution video monitor and
turning the thumbwheel switches to adjust the horizontal and vertical delays until
the deadzones are eliminated.
The timing section 64 sets up and loads the digital data output from the
A/D section 62 into the memory arrays 82 and 84. The address generator 80
loads the digital words into their appropriate memory location in 82 or 84. The
memory arrays 82 and 84 can be standard 120 nano-second dynamic random
access memory or D-RAM. This slow memory can be used only if an
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