Appeal No. 2005-0001
Application No. 09/268,902
bus grid designs before a detailed simulation of the IC layout is made
(footnotes omitted).
We are not convinced by appellant’s argument. We find no limitation in
independent claim 1, which differentiates the claimed method from a method that
makes use of a post-layout simulation. Further, we do not find that Mitsuhashi is
limited to a system that uses a post layout simulation. Mitsuhashi teaches, in
column 11, lines 21-27, and 39-44, that the system should be used in conjunction
with the software that generates the floor plan of the circuit. Thus, we find that
Mitsuhashi teaches that the current analysis should be performed concurrent with
the layout of the integrated circuit.
Appellant argues, on page 11 of the brief, “ Huddleston does not cure the
deficiencies of Mitsuhashi. Huddleston is directed to a method for positioning
bond pads in a semiconductor die layout. Huddleston is concerned with the post-
layout period” (footnotes omitted).
As stated supra, we do not find that the method of claim 1 is limited to a
pre-layout period. Thus, we consider it immaterial for the rejection whether
Huddleston is concerned with either a pre or post layout period.
Appellant argues, on page 12 of the brief, that Huddleston is not
analogous prior art and that “Huddleston does not appear to teach or suggest
accepting information for at least one power zone in the integrated circuit core,
as presently claimed.”
In response, the examiner states, on pages 14 and 15, of the answer:
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