Ex Parte HAVEMANN - Page 2



          Appeal No. 2005-0287                                       Page 2           
          Application No. 09/216,214                                                  

               9.  A transistor gate structure, comprising:                           
                    (a) a gate dielectric over a semiconductor region;                
                    (b) a patterned gate over said gate dielectric                    
               having sidewalls, a top surface and a bottom surface                   
               disposed on said gate dielectric;                                      
                    (c)a lateral growth on said gate dielectric at the                
               corners of said gate, but not under central                            
               regions of said gate, the thickness of said gate                       
               dielectric continually increasing at the                               
               interface of said bottom surface and said sidewalls of                 
               said gate in a direction from said bottom surface                      
               toward and along said sidewalls; and                                   
                    (d) a unitary electrically conductive metallic                    
               material entirely covering said sidewalls and top                      
               surface of said gate.                                                  
               10.  A transistor structure which comprises:                           
                    a region of semiconductor material having a gate                  
               dielectric thereover;                                                  
                    a polysilicon gate disposed over said gate                        
               dielectric having a top, a bottom and sidewalls;                       
                    a silicide layer disposed on said top and                         
               sidewalls of said polysilicon gate; and                                
                    source/drain regions in said region of                            
               semiconductor material spaced apart from each                          
               other, said source/drain regions each disposed                         
               adjacent to and aligned with said silicide layer disposed on said side 
               The prior art references of record relied upon by the                  
          examiner in rejecting the appealed claims are:                              








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