Ex Parte Ng - Page 3

          Appeal No. 2005-0585                                                        
          Application No. 09/821,478                                                  

                                       OPINION                                        
          I. The rejection of claims 1, 3-8, 10-14, and 16-20 under 35                
               U.S.C. § 103 as being unpatentable over Tao in view of Ma              
               and further view of Horak                                              
          We limit our consideration to claims 1 and 4, as stated                     
          supra.                                                                      
          A.  The Examiner’s Position                                                 
               The examiner’s position for this rejection is set forth on             
          pages 5-8 of the answer.  The examiner’s position is summarized             
          below.                                                                      
               The examiner states that the claimed subject matter is                 
          directed to a method of compensating for nested-to-isolated                 
          pattern bias.  Answer, pages 5-6.  The examiner states that                 
          positive bias is compensated for by adding a sputtering                     
          component to the etch chemistry, while negative bias is adjusted            
          for by the electrical bias on the substrate (“space charge”                 
          effect).  Answer, pages 5-6.                                                
               The examiner states that the instant claims recite                     
          providing a structure with a first critical dimension (CD) and              
          lithographically reducing the CD by an O2-containing trimming               
          etch.  The claims further recite correcting the CD-bias between             
          nested and isolated features during a plasma-etch, and also the             
          etching parameters for the process.  Answer, page 6.                        
               The examiner finds that Tao teaches a method for narrowing             
          gate electrodes on a device.  The steps comprise (a) forming a              
          stack layer and patterning the photoresist, (b) optionally                  
          trimming the resist pattern, (c) etching the anti-reflection                
          coating (ARC) and hardmask and trimming the hard mask to a sub-             
          lithographic dimension (if not trimmed by the photoresist), and             
          (d) etching the gate to the desired sub-lithographic dimension.             
          These steps are shown in Figs. 2-6.  The examiner finds that Tao            

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