Appeal No. 2005-0585
Application No. 09/821,478
teach this claimed feature, and we refer to the discussion in
the brief, therein. Brief, pages 10-12.
In summary, appellant states that none of the applied
references acknowledge correcting an existing offset. Appellant
states that the applied references concentrate on preventing any
offset which may occur from a subsequent etching. Appellant
states that clearly the applied references are incapable of
teaching or suggesting compensating for an existing offset.
Brief, pages 11-12.
C. The Examiner’s Rebuttal
The examiner’s response to appellant’s arguments is set
forth below, and is found on pages 8-16 of the answer.
With regard to appellants’ first line of argument
(references would not have been combined), the examiner states
that Tao, Ma, and Horak are analogous art, and solve the same
problem as the appellant’s, i.e., using resist trimming (Tao and
Horak) and space charge effect (Horak and Ma). Answer, page 8.
The examiner explains that appellant recognizes (instant
specification: p.1-p.2, line 8) the criticality of controlling
gate “length” (the width of the polysilicon conductive line
below the gate oxide) of a transistor, and notes that in
achieving a higher density of transistors on a substrate with
smaller dimensions (referred to as “scaling path”), this is even
more critical (instant specification: p.4, line 11-14). The
examiner states that appellant’s invention is directed to a
process to reduce variations in the gate CD in nested and
isolated areas. Answer, page 8-9.
The examiner finds that Tao addresses the same problem of
gate CD control (col. 1, lines 9-14), and teaches that as device
density increases, the criticality of controlling the gate CD
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