Ex Parte Barnett et al - Page 2




             Appeal No. 2005-1295                                                                                      
             Application No. 10/376,682                                                                                

                                                   BACKGROUND                                                          
                    The invention is directed to a single chip embedded microcontroller (e.g., for use                 
             in a smart card) that may communicate with PROM arrays consisting of an OTPROM                            
             (one time programmable read only memory) and an EEPROM (electrically erasable                             
             programmable read only memory).  Representative claim 1 is reproduced below.                              
                    1.      A single chip embedded microcontroller comprising,                                         
                            a processor,                                                                               
                            a first non-volatile erasable PROM array having a communication link with                  
                    said processor, said processor capable of reading, erasing and writing                             
                    information to and from said first non-volatile erasable PROM, wherein said                        
                    erasing of said first non-volatile erasable PROM array is performed on a plurality                 
                    of bytes,                                                                                          
                            a second non-volatile erasable PROM array having a communication link                      
                    with said processor, said processor capable of reading, erasing and writing                        
                    information to and from said second non-volatile erasable PROM, wherein said                       
                    erasing of said second non-volatile erasable PROM array is performed on a                          
                    single byte,                                                                                       
                            a high voltage generator having a communication link with said processor,                  
                    said high voltage generator generating two or more different erase and write                       
                    voltages, and                                                                                      
                            a switch communicating with said high voltage generator, said switch                       
                    connects said two or more different erase and write voltages between said first                    
                    and second non-volatile erasable PROM arrays.                                                      
                    The examiner relies on the following references:                                                   
             Koizumi                            5,504,707                          Apr.  2, 1996                       
             Talreja                            5,742,787                          Apr. 21, 1998                       


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