Appeal No. 2005-1295
Application No. 10/376,682
The rejection seems to rely on Koizumi and only on column 1, lines 43 through
63 of Talreja, with respect to a suggestion to incorporate wear-leveling in flash memory.
The rejection concludes that it would have been obvious to modify the erase/write
voltages to a selected PROM, as taught by Koizumi, to distribute access among flash
memory blocks using wear-leveling techniques, in order to prevent degradation or
failure of particular flash memory cells.
Column 1 of Talreja appears to relate that wear-leveling algorithms distribute
data amongst memory blocks in a flash memory array for extending the number of
programming and erasure cycles for the device; i.e., by apparent avoidance of repeated
reuse of the same memory cells, to the exclusion of others, within an array. We have
no showing in this record of how such algorithms might be applicable to an OTPROM
(having a capability to electrically write information in the prescribed storage area only
one time and no capability to erase; Koizumi col. 1, ll. 6-12). As such, we do not find
suggestion for the combination that is proposed by the rejection.1
CONCLUSION
1 In Koizumi, the EEPROM and OTPROM regions share the same cell structure (col. 4, ll. 3-7).
Consistent with instant claim 1, Koizumi teaches (col. 3, ll. 53-63) that the processor is “capable of”
reading, erasing, and writing to the OTPROM region, although erasing is not performed. We note that
appellants’ OTPROM as disclosed is not precisely “one time” programmable. See, e.g., spec. at 7, ll. 11-
20.
-6-
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