Appeal No. 2005-1295
Application No. 10/376,682
Koizumi apparatus. The reference at the bottom of column 7 states that the voltage
generating circuit “is set” to 0V. As the examiner notes, the output of a 0V signal must
be regulated by the voltage generator. More important, however, appellants do not
explain why -- while the reference expressly indicates that a power supply voltage of 0V
can be generated -- the artisan somehow could not consider a power supply voltage of
0V to be “generated.” We consider the objective teachings of the reference to be a
better indication of the scope of the terms used in the claims, as understood by the
artisan, than post hoc arguments that are contrary to the evidence in the record.
We have also considered appellants’ additional comment in the Reply Brief,
submitting that 0V could not be considered a “high voltage.” The argument is
unavailing, as claim 1 does not require that both (i.e., the minimum of two) of the
generated voltages be relatively high.
We therefore sustain the rejection of claims 1-5 and 8-13 under 35 U.S.C. § 102
as being anticipated by Koizumi.
Appellants’ arguments in response to the rejection of claims 6 and 14 under 35
U.S.C. § 103 as being unpatentable over Koizumi and Talreja are minimal. However,
we cannot sustain the rejection because we find that a prima facie case for obviousness
has not been established. The claims (e.g., claim 6) require that the operating system
alternately provides the two or more different erase and write voltages to the OTPROM
and the PROM array.
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